ABOUT PROJECTS CONTACT

Kalindu Wijerathna

Full Stack Software Engineer (Java|Springboot|React|Node)
DevOps Engineer
Networking, SDN & NLP Research Enthusiast

ResumeResume

(UG)Bsc.Eng(Hons) University of Peradeniya
Specializing in Computer Engineering

Oval Image 1 Oval Image 2 Oval Image 3

Research & Projects

Intent-Based SDN

NLP-Driven Intent-Based SDN Architecture

Final Year Research

Designing a layered architecture to interpret high-level intents using NLP for dynamic SDN configurations.
Includes automated topologies via Mininet/Containernet, ONOS integration with Grafana/Prometheus, and NLP server/API deployment.
NLP pipeline is driven by a multi-agentic RAG pipeline with a custom NER for Network Entity Recognition. Dec 2024 – Present
πŸ”— Project Page
πŸ’» View on GitHub

Digital Signage

Digital Signage CMS System for IT Center UoP

3 Member Group

Centralized CMS for automated display content. Used React, TypeScript, PHP APIs with GitHub CI/CD.
Replaced manual scheduling with dynamic, rule-based content display tailored for academic needs.
Aug 2023 – Jan 2024
Officially deployed – Jan 2024
πŸ”— Project Page
πŸ’» View on GitHub
πŸ… Certificate of Appreciation from University

Academetrix

Academetrix: Student Result Management Portal

8 Member Group

Developed a secure, role-based full-stack student result portal using Java (Spring Boot), MySQL, and Tailwind CSS.
Built RESTful APIs for authentication and result management, with role-specific access for admins, staff, and students.
Deployed on AWS EC2 using Jenkins CI/CD, Terraform for infrastructure, and Ansible for server provisioning.
Apr 2024 – Dec 2024

πŸ’» View on GitHub

Pera Link

Pera Link – Social Platform

3 Member Group

Social media tailor-made for Pera University community, with backend in Express.js & MySQL and frontend in Vue.js. Earlier this year our original undergraduate project idea of this was adopted by HackersClub UoP as the first long-term University-wide project involving all the faculties and batches.
May 2023 – Aug 2023;
Lead DevOps – Dec 2024 – Present

πŸ”— Project Page
πŸ’» View on GitHub

Digital Twin

Digital Twin of a Smart City Traffic Flow Intersection

14 Member Group

Developed a Digital Twin system to simulate and analyze real-time traffic flow at intersections using Apache Kafka, Unity-3D, Docker, and Kubernetes.
Designed and implemented core system architecture, focusing on scalable microservices and real-time data pipelines.
Led Kafka-based communication layer for synchronized sensor-to-simulator messaging and containerized services orchestrated via Kubernetes for deployment and scaling.
Apr 2024 – Nov 2024
πŸ’» View on GitHub

Pera Swarm SCARA

SCARA: Pera Swarm Modular Robots

5 Member Group

Designed and developed a modular SCARA robotic arm as part of the long-running Pera Swarm initiative, focusing on swarm-capable, scalable robotic units.
Integrated Raspberry Pi Zero-W and ATtiny85 for embedded control, and implemented full-stack support using MongoDB, Express.js, React.js, and Node.js.
Led the development of the database architecture and contributed to backend APIs and documentation, including user and engineering manuals.
Part of Pera Swarm Project
Oct 2023 - Jan 2024
πŸ”— Project Page
πŸ’» View on GitHub
πŸ“š Pera Swarm Research Projects

Elective Recommender

Elective Course & Field Recommendation System

5 Member Group

Developed an intelligent Elective Course Recommendation System using machine learning models including SVM, LDA, and Multilayer Perceptron (MLP).
Designed and implemented the overall system architecture, and established a complete MLOps pipeline using ZenML for reproducible experimentation and streamlined model lifecycle management.
Deployed the solution on Google Cloud Platform, integrating model serving, storage, and performance monitoring.
Actively contributed to data preprocessing, training pipeline, evaluation metrics, and scalable deployment strategies.
Mar 2024 – Aug 2024
πŸ’» View on GitHub

RISC-V CPU

8-bit Single Cycle RISC-V CPU

2 Member Group

Designed and implemented an 8-bit single-cycle CPU from scratch using Verilog, adhering to the RISC-V architecture.
Integrated key components such as the Arithmetic Logic Unit (ALU), register file, control unit, and memory hierarchy, ensuring correct instruction decoding and execution.
Jun 2023 – Aug 2023
πŸ’» View on GitHub

"Kalindu here β€” AyubowanπŸ™!"

I'm a Passionate and Creative tech enthusiast with a strong work ethic, dedicated to building intelligent, scalable systems across the full stack and beyond.

Full Stack Software Engineer | DevOps Engineer | Networking, SDN, NLP Research Explorer.

BScEngHons in Computer Engineering

Mar 2021 – Present

University of Peradeniya

Current CGPA: 3.60 / 4.00

GCE Advanced Level (A | A | A)

2019

Dharmaraja College, Kandy

Z-Score: 2.164

Cisco Certified Network Associate (CCNA 200-125)

2020

Specializations

Certificate Icon

AWS Cloud Solutions Architect Professional Specialization (2024)

AWS | Coursera β€” 4 Course Specialization
Certificate Icon

Java Spring Framework Specialization (2025)

LearQuest | Coursera β€” 4 Course Specialization
Certificate Icon

Meta Front-End Developer Certificate (React) (2025)

Meta | Coursera β€” 9 Course Specialization
Certificate Icon

Architecting with Google Kubernetes Engine Specialization (2025)

Google | Coursera β€” 3 Course Specialization
Certificate Icon

Certified Kubernetes Application Developer (CKAD) (2025)

LearnKartS | Coursera β€” 3 Course Specialization
Certificate Icon

Advanced Diploma in Computer Networks & Internet Protocol (2024)

NPTEL, India & Alison, Ireland

Certifications

Let's Connect πŸ₯‚
To Build Something Awesome

Email: wijerathnakalindu@gmail.com

Location: Kandy, Sri Lanka

LinkedIn: linkedin.com/in/kalinduwijerathna